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16- bit, 2 m sps/1 msps, precision, differential sar adc s data sheet ad4001 / ad4005 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any paten t or patent rights of analog devices. trademarks and registered trademarks are the prop erty of their respective owners one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features throughput: 2 msps/1 msps options inl: 0 .4 lsb maximum guaranteed 1 6 - bit no missing codes low power 9.5 mw at 2 msps, 4.9 mw at 1 msps (vdd only) 80 w at 10 ksps, 16 mw at 2 msps (total) s nr : 96.2 db typical at 1 k hz, v ref = 5 v; 95.5 db typical at 100 k hz thd : ? 1 23 db typical at 1 k hz , v ref = 5 v; ? 99 db typical at 1 00 k hz ease of use features reduce system power and complexity input o ver v oltage c lamp circuit reduced n on linear i nput charge kick back high - z m ode long acquisition phase input s pan c ompression fast conversion time allows l ow sp i clock rates spi - programmable modes, r ead/ w rite capability , s tatus w ord d ifferen tial analog input range: v ref 0 v to v ref wi th v ref from 2 .4 v to 5. 1 v single 1.8 v s upply operation with 1.71 v to 5.5 v logi c interface sar architecture : n o latency/pipeline delay , valid first conversion first accurate conversion guaranteed o peration : ?40c to + 125c spi - /qspi - /microwire - /dsp - compatible serial interface ability to daisy - chain multiple adcs and busy indicator 10- lead packages: 3 mm 3 mm lfcsp , 3 mm 4.90 mm msop applications automatic t est e quipment machine a utomation medical e quipment battery - powered equipment precision d ata acquisition systems general description the ad4001 / ad4005 are low noise, low power, high speed , 1 6 - bit, precision successive approximation register (sar) analog - to - digita l converter s (adc s) . the ad4001 offers a 2 msps throughput , and the ad4005 offers a 1 msps throughput. they incorporate ease of use features that reduce signal chain power consumption , reduce signal chain complexity , and enable higher channel density. the high - z mode , coupled with a long acquisition phase , eliminates the need for a dedicated high power, high speed adc driver, thus broadening the range of low power precision amplifiers that can drive these adcs directly , while still achieving optimum performance. the input span compression feature enables the adc driver amplifier and the adc to operate off common supply rails without the need for a negative supply while preserving the full adc code range. the low serial peripheral interface ( s pi ) clock rate requirement reduces the digital input/output power consumption, broadens processor options , and simplifies the task of sending data across digital isolation. operating from a 1.8 v supply, the ad4001 / ad4005 have a v ref fully differential input range with v ref ranging from 2.4 v to 5.1 v. the ad4001 consume s only 16 mw at 2 msps with a minimum sck rate of 70 mh z in turbo mode , and the ad4005 consumes only 8 mw at 1 msps . the ad4001 / ad4005 both achieve 0.4 lsb integral nonlinearity error (inl) maximum, guaranteed no missing codes at 16 bits with 96.2 db typical signal - to - noise ratio (snr) for 1 khz inputs . the reference voltage is applied externally and can be set independent ly of the supply voltage. the spi - compatible , versatile serial interface features seven different modes including the ability, using the sdi input, to daisy - chain several adcs on a single 3 - wire bus , and provides an optional busy indicator. the ad4001 / ad4005 are compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad4001 / ad4005 are available in a 10 - lead msop or lfcsp with operation specified from ?40c to +125c . the device s are pin compatible with the 18- bit, 2 msps ad4003 (see table 8 ) . functional block dia gram gnd in+ in? sdi sck sdo cnv ad4001/ ad4005 16-bit sar adc serial interface vio ref vdd v ref 0 v ref 0 v ref /2 v ref /2 high-z mode clamp span compression turbo mode status bits 2.4v to 5.1v 1.8v 10f 1.8v to 5v 3-wire or 4-wire spi interface (daisy chain, cs) 15368-001 figure 1 .
ad4001/ad4005 data sheet rev. b | page 2 of 37 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revi sion history ............................................................................... 2 specifications ..................................................................................... 4 timing specifications .................................................................. 7 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 11 terminology .................................................................................... 16 theory of operat ion ...................................................................... 17 circuit information .................................................................... 17 converter operation .................................................................. 18 transfer functions ...................................................................... 18 applications information .............................................................. 19 typical application diagrams .................................................. 19 analog inputs ............................................................................. 20 driver amplifier choice ........................................................... 22 ease of drive features ............................................................... 23 voltage reference input ............................................................ 24 power supply ............................................................................... 24 digital interface .......................................................................... 25 register r ead/write functionality ........................................... 26 status word ................................................................................. 28 cs mode, 3 - wire tur b o mo d e ................................................. 29 cs mode, 3 - wire without busy indicator ............................. 30 cs mode, 3 - wire with busy indicator .................................... 31 cs mode, 4 - wire tur b o mo d e ................................................. 32 cs mode, 4 - wire without busy indicator ............................. 33 cs mode, 4 - wire with busy indicator .................................... 34 daisy - chain mode ..................................................................... 35 layout guidelines ....................................................................... 36 evaluating the ad4001/ad4005 performance .......................... 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 37 revision history 8 /2017 rev. a to rev. b changes to general description section ...................................... 1 changes to table 1 ............................................................................ 6 changes to endnote 3 , table 2 ........................................................ 7 changes to table 4 ............................................................................ 8 change to pin 3 description and pin 4 description , table 7 ... 10 reorganize d typical performance characteristics section ...... 1 3 changes to figure 1 7 , figure 19, and figure 2 1 ......................... 1 3 added figure 2 3 ; renumbered sequentially .............................. 1 4 changes to figure 2 7 ...................................................................... 1 5 changes to circuit information section and table 8 ................ 1 7 changes to endnote 1 and endnote 2, table 9 ........................... 1 8 changes to figure 37 caption and rc filter va lu e s section ... 2 1 changes to high frequency input signals section, figure 38 caption, and figure 3 9 caption ................................................... 2 2 added multiplexed application s section and figure 4 0 ........... 2 2 changes to figure 4 1 and figure 42 caption ............................. 2 3 changes to figure 4 3 , figure 44 caption, figure 4 5 , and voltage reference input section ................................................................. 2 4 chan ges to power supply section, figure 46 , figure 47, digital interface section, and table 11 ..................................................... 2 5 changes to cs mode, 3 - wire turbo mode section ................... 2 9 changes to cs mode, 3 - wire with busy induction section and figure 56 .......................................................................................... 3 1 changes to cs mode, 4 - wire turbo mode section and figure 58 .......................................................................................... 3 2 changes to cs mode, 4 - wire with busy indicator section and figure 6 2 .......................................................................................... 3 4 4 /2017 rev. 0 to rev. a added ad4005 ................................................................... universal changes to title, features section , general description section , and figure 1 ........................................................................................ 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 6 changes to table 4 ............................................................................. 7 changes to figure 19 caption and figure 21 ............................. 12 changes to figure 24 ...................................................................... 13 added figure 25; renumbered sequentially .............................. 13 changes to circuit information sect ion and table 8 ................ 1 6 changes to rc filter values section ............................................ 20 changes to high frequency input signals section .................... 2 1 changes to high - z mode section and figure 41 ....................... 2 2 changes to long acquisition phase section .............................. 23 changes to digital interface section and register read /write functionality section ..................................................................... 2 4 changes to cs mode, 3 - wire turbo mode section .................. 2 7 changes to cs mode, 4 - wire tur b o mo de section .................. 30
data sheet ad4001/ad4005 rev. b | page 3 of 37 changes to layout guidelines section and evaluating the ad400 1 /ad400 5 performance section ....................................... 3 4 updated outline dimensions ........................................................ 3 5 changes to ordering guide ........................................................... 3 5 1/ 2017 rev ision 0 : initial version
ad4001/ad4005 data sheet rev. b | page 4 of 37 specifications vdd = 1.71 v to 1.89 v , v io = 1. 71 v to 5 .5 v, v ref = 5 v, all specifications t min to t max , h igh - z m ode disabled, span compression disabled , turbo mode enabled , and sampling frequency (f s ) = 2 msps for the ad4001 and f s = 1 msps for the ad4005 , unless otherwise note d. table 1. parameter test conditions/comments min typ max unit resolution 1 6 bits analog input voltage range v in+ ? v in? ?v ref +v ref v span c ompression enabled ?v ref 0. 8 +v ref 0. 8 v operating input voltage v in+ , v in? to gnd ?0.1 v ref + 0.1 v span c ompression enabled 0.1 v ref 0.9 v ref v common - mode input range v ref /2 ? 0.125 v ref /2 v ref /2 + 0.125 v common - mode rejection ratio ( cmrr) f in = 500 khz 68 db analog input current acquisition phase , t = 25c 0.3 na high - z mode enabled , converting dc input at 2 msps 1 a throughput complete cycle ad4001 500 ns ad4005 1000 ns conversion time 290 320 ns acquisition phase 1 ad4001 290 ns ad4005 790 ns throughput rate 2 ad4001 0 2 msps ad4005 0 1 msps transient response 3 250 ns dc accuracy no missing codes 16 bits integral nonlinearity error (inl) ?0.4 0.2 +0.4 lsb differential nonlinearity error (dnl) ?0.5 0.2 +0.5 lsb transition noise 0.35 lsb zero error ?1.5 0.1 +1.5 lsb zero error drift 4 ?0.28 +0.28 ppm/c gain error ?16.5 0.4 +16.5 lsb gain error drift 4 ?0.23 +0.23 ppm/c power supply sensitivity vdd = 1.8 v 5% 0.25 lsb 1/f noise 5 bandwidth = 0.1 hz to 10 hz 6 v p -p ac accuracy dynamic range 96.3 db total rms noise 54 v rms f in = 1 khz, ?0.5 dbfs, v ref = 5 v signal -to - noise ratio (snr) 95.6 96.2 db spurious - free dynamic range (sfdr) 122 db total harmonic distortion (thd) ?123 db signal -to - noise - and - distortion ratio (sinad) 95.5 96 db oversampled dynamic range oversampling ratio (osr) = 256, v ref = 5 v 120 db
data sheet ad4001/ad4005 rev. b | page 5 of 37 parameter test conditions/comments min typ max unit f in = 1 khz, ?0.5 dbfs, v ref = 2.5 v snr 92.1 93.2 db sfdr 118 db thd ?117 db sinad 92 93 db f in = 100 khz, ?0.5 dbfs, v ref = 5 v snr 95.5 db thd ?99 db sinad 93.8 db f in = 400 khz, ?0.5 dbfs, v ref = 5 v snr 91 db thd ?92 db sinad 89 db ?3 db input bandwidth 10 mhz aperture delay 1 ns aperture jitter 1 ps rms reference voltage range , v ref 2.4 5.1 v current v ref = 5 v ad4001 2 msps 1.1 ma ad4005 1 msps 0.5 ma input overvoltage clamp in+/in? current, i in+ /i in? v ref = 5 v 50 ma v ref = 2.5 v 50 ma v in+ /v in? at maximum i in+ /i in? v ref = 5 v 5.4 v v ref = 2.5 v 3.1 v v in+ /v in? clamp on/off threshold v ref = 5 v 5.25 5.4 v v ref = 2.5 v 2.68 2.8 v deactivation time 360 ns ref current at maximum i in+ /i in? v in+ /v in? > v ref 100 a digital inputs logic levels input low voltage, v il vio > 2.7 v ?0.3 +0.3 vio v vio 2.7 v ?0.3 +0.2 vio v input high voltage, v ih vio > 2.7 v 0.7 vio vio + 0.3 v vio 2.7 v 0.8 vio vio + 0.3 v input low current, i il ?1 +1 a input high current, i ih ?1 +1 a input pin capacitance 6 pf digital outputs data format serial 16 bits, twos complement pipeline delay conversion results available immediately after completed conversion output low voltage, v ol i sink = 500 a 0.4 v output high voltage, v oh i source = ?500 a vio ? 0.3 v power supplies vdd 1.71 1.8 1.89 v vio 1.71 5.5 v standby current vdd = 1.8 v, vio = 1.8 v, t = 25c 1.6 a
ad4001/ad4005 data sheet rev. b | page 6 of 37 parameter test conditions/comments min typ max unit power dissipation vdd = 1.8 v, vio = 1.8 v, v ref = 5 v 10 ksps, high - z mode disabled 80 w 1 msps, high - z mode disabled 8 9.3 mw 2 msps, high - z mode disabled 16 18.5 mw 1 msps, high - z mode enabled 10 12.3 mw 2 msps, high - z mode enabled 20 24.5 mw vdd only 1 msps, high - z mode disabled 4.9 mw 2 msps, high - z mode disabled 9.5 mw ref only 1 msps, high - z mode disabled 2.8 mw 2 msps, high - z mode disabled 5.5 mw vio only 1 msps, high - z mode disabled 0.4 mw 2 msps, high - z mode disabled 1.0 mw energy per conversion 8 nj/sample temperature range specified performance t min to t max ?40 +125 c 1 the acquisition phase is the time available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 2 ms ps for the ad4001 and 1 msps for the ad4005 . 2 a throughput rate of 2 msps can only be achieve d with turbo mode enabled and a minimum sck rate of 70 mhz. re f er to table 4 for the maximum ac hievable throughput for different modes of operation. 3 transient response is the time required for the adc to acquire a full - scale input step to 1 lsb accuracy. 4 the minimum and maximum values are guaranteed by characterization , but not production tested. 5 see the 1/f noise plot in figure 23.
data sheet ad4001/ad4005 rev. b | page 7 of 37 timing specification s vdd = 1.71 v to 1.89 v , vio = 1.71 v to 5.5 v , v ref = 5 v , all specifications t min to t max , high - z mode disabled, span compression disabled , turbo mode enabled , and sampling frequency (f s ) = 2 msps for the ad4001 and f s = 1 msps for the ad4005 , unless otherwise noted . see figure 2 for the timing voltage levels. table 2. digital interface timing parameter symbol min typ max unit conversion time cnv rising edge to data available t conv 270 290 320 ns acquisition phase 1 t acq ad4001 290 ns ad4005 790 ns time between conversions t cyc ad4001 500 ns ad4005 1000 ns cnv pulse width ( cs mode) 2 t cnvh 10 ns sck period ( cs mode) 3 t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck period (daisy - chain mode) 4 t sck vio > 2.7 v 20 ns vio > 1.7 v 25 ns sck low time t sckl 3 ns sck high time t sckh 3 ns sck falling edge to data remains valid delay t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv o r sdi low to sdo d15 most significant bit (msb) valid delay ( cs mode) t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns cnv rising edge to first sck rising edge delay t quiet1 190 ns last sck falling edge to cnv rising edge delay 5 t quiet2 60 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 2 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sck valid hold time from cnv rising edge (daisy - chain mode) t hsckcnv 12 ns sdi valid setup time from sck rising edge (daisy - chain mode) t ssdisck 2 ns sdi valid hold time from sck rising edge (daisy - chain mode) t hsdisck 2 ns 1 the acquisition phase is the t ime available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 2 msps for the ad4001 and 1 msps for the ad4005 . 2 for turbo mode, t cnvh must match the t quiet1 minimum. 3 a throughput rate of 2 msps can only be achieved with turbo mode enabled and a minimum sck rate of 70 mhz. refer to table 4 for the maximum achievable throughput for different modes of op eration. 4 a 50% duty cycle is assumed for sck. 5 see figure 22 f or sinad vs. t quiet2 . x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 2.7v, x = 80, and y = 20; for vio > 2.7v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 1. 15368-002 figure 2 . voltage levels for timing
ad4001/ad4005 data sheet rev. b | page 8 of 37 table 3 . register read/write timing parameter symbol min typ max unit read/write operation cnv pulse width 1 t cnvh 10 ns sck period t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck low time t sckl 3 ns sck high time t sckh 3 ns read operation cnv low to sdo d1 5 msb valid delay t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns sck falling edge to data remains valid t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv r ising e dge to sdo high impedance t dis 20 ns write operation sdi valid setup time from sck rising edge t ssdisck 2 ns sdi valid hold time from sck rising edge t hsdisck 2 ns cnv rising edge to sck edge hold time t hcnvsck 0 ns cnv falling edge to sck active edge setup time t scnvsck 6 ns 1 for turbo mode, t cnvh must match the t quiet1 minimum. table 4 . achievable throughput for different modes of operation parameter test conditions/comments min typ max unit throughput , cs mode 3- wire and 4 - wire turbo mode f sck = 100 mhz, vio 2.7 v 2 msps f sck = 80 mhz, vio < 2.7 v 2 msps 3- wire and 4 - wire turbo mode and six status bits f sck = 100 mhz, vio 2.7 v 2 msps f sck = 80 mhz, vio < 2.7 v 1.86 msps 3- wire and 4 - wire mode f sck = 100 mhz, vio 2.7 v 1.82 msps f sck = 80 mhz, vio < 2.7 v 1.69 msps 3- wire and 4 - wire mode and six status bits f sck = 100 mhz, vio 2.7 v 1.64 msps f sck = 80 mhz, vio < 2.7 v 1.5 msps
data sheet ad4001/ad4005 rev. b | page 9 of 37 absolute maximum ratings note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time . table 5. parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0. 4 v or 50 ma supply voltage ref , vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to + 2.1 v vdd to vio ?6 v to +2.4 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature soldering 260c reflow as per jedec j - std -020 esd ratings human body model 4 kv machine model 200 v field induced charged device model 1.25 kv 1 see the analog inputs section for an explanation of in+ and in?. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance t hermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 6 . thermal resistance package type 1 ja 2 jc 3 unit rm -10 147 38 c/w cp - 10 - 9 114 33 c/w 1 test condition 1: thermal impedance simulated values are based upon use of 2s2p jedec pcb. see the ordering guide . 2 ja is the natural convection junction - to - ambient thermal resistance measured in a one cubic foot sealed enclosure. 3 jc is the junction - to - case thermal resistance. esd caution
ad4001/ad4005 data sheet rev. b | page 10 of 37 pin configurations and function descript ions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad4001/ ad4005 top view (not to scale) 15368-003 figure 3 . 10 - lead msop pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9 sdi 8 sck 7 sdo 6 cnv notes 1. connect the exposed pad to gnd. this connection is not required to meet the specified performance. 15368-004 ad4001/ ad4005 top view (not to scale) figure 4 . 10 - lead lfcsp pin configuration table 7 . pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the v ref range is 2 .4 v to 5 .1 v. this pin is referred to the gnd pin and must be decoupled closely to the gnd pin with a 10 f, x7r ceramic capacitor. 2 vdd p 1.8 v power supply. the vdd range is 1.71 v to 1.89 v. bypass vdd to gnd with a 0.1 f ceramic capacitor. 3 in+ ai differential positive analog input. see the differential input considerations section. 4 in? ai differential negative analog input. see the differential input considerations section. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the devi ce : daisy - chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in daisy - chain mode, the data is read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the ad c as follows : daisy -c hain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 1 6 sck cycle s. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. with cnv low, the device can be programmed by clocking in a 16 - bit word on sdi on the rising edge of sck. 10 vio p input/output interface digital power. nominally, this pin is at the same supply as the host interfa ce (1.8 v , 2.5 v, 3 v, or 5 v). bypass v io to gnd with a 0.1 f ceramic capacitor. n/a 2 epad p exposed pad (lfcsp only). connect the exposed pad to gnd. this connection is not required to meet the specified performance. 1 ai is analog input, p is power , di is digital input, and do is digital output. 2 n/a means not applicable.
data sheet ad4001/ad4005 rev. b | page 11 of 37 typical performance characteristics vdd = 1.8 v , vio = 3.3 v , v ref = 5 v , t = 25c, high - z mode disabled, span compression disabled , t urbo mode enabled , and sampling frequency ( f s ) = 2 msps for the ad4001 and f s = 1 msps for the ad4005 , unless otherwise noted. ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 in l (lsb) code ?4 0 c +2 5 c +12 5 c 15368-200 figure 5 . inl vs. code for various temperatures, v ref = 5 v code ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 in l (lsb) ?4 0 c +2 5 c +12 5 c 15368-201 figure 6 . inl vs. code for various temperatures, v ref = 2.5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 in l (lsb) code high-z enabled span compression enabled 15368-407 figure 7 . inl vs. code, high - z and span compression modes enabled, v ref = 5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 dn l (lsb) code ?40 c +2 5 c +12 5 c 15368-203 figure 8 . dnl vs. code for various temperatures, v ref = 5 v code ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 dnl (lsb) ?4 0 c +2 5 c +12 5 c 15368-204 figure 9 . dnl vs. code for various temperatures, v ref = 2.5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 dn l (lsb) code high-z enabled span compression enabled 15368-410 figure 10 . dnl vs. code, high - z and span compression modes enabled, v ref = 5 v
ad4001/ad4005 data sheet rev. b | page 12 of 37 15368-205 0 200000 400000 600000 800000 1000000 1200000 32766 32767 32768 32769 32770 code count code v ref = 5v v ref = 2.5v figure 11 . histogram of a dc input at code center, v ref = 2.5 v and v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 1m frequency (hz) v ref = 5v snr = 96.25db thd = ?124.30db sinad = 96.23db 15368-207 figure 12 . 1 khz, 0.5 dbfs input tone fft, wide view, v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 1m frequency (hz) v ref = 5v snr = 95.48db thd = ?98.63db sinad = 93.84db 15368-210 figure 13 . 100 khz, 0.5 dbfs input tone fft, wide view 15368-208 0 100000 200000 300000 400000 500000 600000 32766 32767 32768 32769 32770 code count code v ref = 5v v ref = 2.5v figure 14. histogram of a dc input at code transition, v ref = 2.5 v and v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 1m frequency (hz) v ref = 2.5v snr = 93.12db thd = ?118.26db sinad = 93.11db 15368-209 figure 15 . 1 khz, 0.5 dbfs input tone fft, wide view, v ref = 2.5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 1m frequency (hz) v ref = 5v snr = 91.04db thd = ?91.47db sinad = 88.85db 15368-213 figure 16 . 400 khz, 0.5 dbfs input tone fft, wide view
data sheet ad4001/ad4005 rev. b | page 13 of 37 15368-219 92.5 93.0 93.5 94.0 94.5 95.0 95.5 96.0 96.5 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 snr, sinad (db) reference vo lt age (v) enob (bits) enob snr sinad figure 17 . snr, sinad, and enob vs. reference voltage, f in = 1 khz 15.63 15.64 15.65 15.66 15.67 15.68 15.69 15.70 15.71 15.72 15.73 95.9 96.0 96.1 96.2 96.3 96.4 96.5 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) enob (bits) srn, sinad (db) snr sinad enob 15368-222 figure 18 . snr, sinad, and enob vs. temperature, f in = 1 khz 15368-212 95 100 105 110 115 120 125 130 1 2 4 8 16 32 64 128 256 1024 512 snr (db) decimation rate dynamic range frequency = 1khz frequency = 10khz figure 19 . snr vs. decimation rate for va rious input frequencies, 2 msps 15368-216 ?132 ?130 ?128 ?126 ?124 ?122 ?120 ?118 ?116 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 120 121 122 123 124 125 126 127 128 129 reference vo lt age (v) thd (db) sfdr (db) sfdr thd figure 20 . thd and sfdr vs. reference voltage, f in = 1 khz 126.3 126.4 126.5 126.6 126.7 126.8 126.9 127.0 127.1 ?129 ?128 ?127 ?126 ?125 ?124 ?123 ?122 ?121 ?120 ?119 ?118 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) sfdr (db) thd (db) thd sfdr 15368-225 figure 21 . thd and sfdr vs. temperature, f in = 1 khz 15368-215 89 90 91 92 93 94 95 96 97 0 20 40 60 80 100 sinad (db) t quiet2 (ns) vio = 1.89v vio = 3.6v vio = 5.5v figure 22 . sinad vs. t quiet2
ad4001/ad4005 data sheet rev. b | page 14 of 37 60 58 55 56 59 57 54 adc output reading (v) 0 9 8 5 6 7 4 3 2 1 10 time (seconds) 15368-217 figure 23 . 1/f noise for 0.1 hz to 10 hz bandwidth, 50 ksps, 2500 samples averaged per reading 8 7 3 5 6 4 1 2 0 operating current (ma) vdd high-z disabled vdd high-z enabled ref high-z disabled ref high-z enabled vio high-z disabled vio high-z enabled ?40 100 80 60 40 20 0 ?20 120 temperature (c) 15368-223 figure 24 . operating current vs. temperature, ad4001 , 2 msps 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?40 ?20 0 20 40 60 80 100 120 zero error, gain error (lsb) temper a ture (c) zero error pfs error nfs error 15368-221 figure 25 . zero error and gain error vs. temperature, positive full scale (pfs) and negative full scale (nfs) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?40 ?20 0 20 40 60 80 100 120 oper a ting current (ma) temperature (c) vdd high-z enabled vdd high-z disabled ref high-z enabled ref high-z disabled vio high-z enabled vio high-z disabled 15368-325 figure 26 . operating current vs. temperature, ad4005 , 1 msps
data sheet ad4001/ad4005 rev. b | page 15 of 37 15368-218 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 reference current (ma) reference voltage (v) 2msps 1msps figure 27 . reference current vs. reference voltage 23 21 13 17 19 15 9 11 7 5 t dsdo (ns) 0 100 80 60 40 200 180 160 140 20 220 120 load capacitance (pf) vio = 5v vio = 3.3v vio = 1.8v 15368-224 figure 28 . t dsdo vs. load capacitance 25.0 20.0 10.0 15.0 5.0 22.5 17.5 7.5 12.5 2.5 0 standby current ( a) ?40 100 80 60 40 20 0 ?20 120 temperature (c) 15368-226 figure 29 . standby current vs. temperature
ad4001/ad4005 data sheet rev. b | page 16 of 37 terminology integral nonlinearity error (inl) inl is the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the l ast code transition. the deviation is measured from the middle of each code to the true straight line (see figure 31). differential nonlinearity erro r (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01) occurs at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition an d the actual level of the first transition from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective numb er of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: enob = ( sinad db ? 1.76)/6.02 enob is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five h armonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. the value for dynamic range is expressed in decib els. it is measured with a signal at ?60 dbfs so that it includes all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noi se - and - distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and whe n the input signal is held for a conversion. transient response transient response is the time required for the adc to acquire a full - scale input step to 1 lsb accuracy. common - mode rejection ratio (cmrr) cmrr is the ratio of the power in the adc output a t the frequency, f, to the power of a 200 mv p - p sine wave applied to the common - mode voltage of in+ and in? of frequency, f. cmrr (db) = 10log( p adc_in / p adc_out ) where: p adc_in is the common - mode power at the frequency, f, applied to the in+ and in? inputs . p adc_out is the power at the f requency, f, in the adc output. power supply rejection ratio (psrr) psrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the adc vdd supply of frequency, f. psrr (db) = 10 log( p vdd_in / p adc_out ) where: p vdd_in is the power at the frequency, f, at the vdd pin. p adc_out is the power at the frequency, f, in the adc output.
data sheet ad4001/ad4005 rev. b | page 17 of 37 theory of operation 15368-007 comp control logic switches control busy output code cnv c c 2c 16,384c 4c 32,768c lsb sw+ msb lsb sw? msb c c 2c 16,384c 4c 32,768c in+ ref gnd in? figure 30 . adc simplified schematic circuit information the ad4001 / ad4005 are high speed , low power, single - supply, precise, 1 6 - bit adc s based on a sar architecture. the ad4001 is capable of converting 2 ,0 00,000 samples per second (2 msps) , the ad4005 is capable of converting 1 ,000,000 samples per second ( 1 msps) . the power consumption of the ad4001 / ad4005 scales with throughput because they power down in between conversions. when ope rating at 10 ksps, for example, they typically consume 80 w , making them ideal for battery - powered applications . the ad4001 / ad4005 also have a valid first conversion after being powered down for long periods , which can further reduce power consumed in applications in which the adc does not need to be constantly converting . the ad4001 / ad4005 provide the user with a n on - chip track - and - hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. the ad4001 / ad4005 incorporate a multitude of unique ease of use features that r esult in a lower system power and footprint . the ad4001 / ad4005 each ha ve an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. the analog input incorporates circuitry that reduces the nonlinear charge kick back seen from a t ypical switched capacitor sar input . th is reduction in kickback , combined with a longer acquisition phase , means reduced settling requirements on the driving amplifier . this combination allows the use of lower bandwidth and lower power amplifiers as drivers. it has the additional benefit of all owing a larger resistor value in the input rc filter and a corresponding smaller capacitor , which results in a smaller rc load for the amplifier , improving stability and power dissipation. h igh - z m ode can be enabled via the spi interface by programmin g a register bit (see table 14) . when h igh - z m ode is enabled , the adc input has a low input charging current at low input signal frequencies , as well as improved distortion over a wide frequenc y range up to 100 k hz . for frequencies greater than 100 k hz and multiplexing , disable h igh - z mode. for single - supply applications , a span compression feature creates additional headroom and footroom for the drivi ng amplifier to access the full range of the adc. the fast conversion time of the ad4001 / ad4005 , along with turbo mode , allow s low clock rates to read back conversions even when runnin g at their maximum throughput rates of 2 msps / 1 msps . note that , for the ad4001 , a throughput rate of 2 msps can be achieved only with turbo mode enabled. the ad4001 / ad4005 can interfac e with any 1.8 v to 5 v digital logic family. they are available in a 10 - lead msop or a tiny 10- lead l fcsp that allows space savings and flexible configurations. the ad4001 / ad4005 are pin for pin compatible with some of the 14 - /16 - /18 - /20 - b it p recision sar adcs listed in table 8 . table 8. msop and lfcsp 14- /16 - /18- /20- bit precision sar adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps 20 1 ad4020 2 18 1 ad7989 - 1 2 ad7691 2 ad7690 2 , ad7989 - 5 2 , ad4011 2 ad4003 2 , ad4007 2 , ad7982 2 , ad7984 2 16 1 ad7684 ad7687 2 ad7688 2 , ad7693 2 , ad7916 2 ad4001 , ad4005 , ad7915 2 16 3 ad7680 , ad7683 , ad7988 - 1 2 ad7685 2 , ad7694 ad7686 2 , ad7988 - 5 2 ad4000 2 , ad4004 2 , ad7980 , 2 ad7983 2 14 3 ad7940 ad7942 2 ad7946 2 not applicable 1 true differential. 2 pin for pin compatible. 3 pseudo differential.
ad4001/ad4005 data sheet rev. b | page 18 of 37 converter operation the ad4001 / ad4005 are sar - based adc s using a charge redistribution sampling digital - to - analog converter ( dac ). figure 30 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitor s , which are connected to the comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via the sw+ and sw? switches . all independent switches connect the other terminal of each capacitor to the analog inputs. t herefore, the capacitor arrays are used as sampling capacitors and acquire the analog si gnal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase initiate s . when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. t he differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator input s, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and v ref , the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 , , v ref / 65,536 ). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and a busy signal indicator. because the ad4001 and the ad4005 have on - board conversion clock s , the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfe r characteristic s for the ad4001 / ad4005 are shown in figure 31 and table 9 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 15368-008 figure 31 . adc ideal transfer function (fsr is full - scale range) table 9 . output codes and ideal input voltages description analog input, v ref = 5 v v ref = 5 v with span compression enabled digital output code (hex) + fsr ? 1 lsb +4.999847 v +3.999878 v 0x7fff 1 midscale + 1 lsb +152.6 v +122.1 v 0x0001 midscale 0 v 0 v 0x0000 midscale ? 1 lsb ?152.6 v ?122.1 v 0xffff ?fsr + 1 lsb ?4.999847 v ?3.999878 v 0x8001 ?fsr ?5 v ?4 v 0x8000 2 1 this output code is also the code for an overranged analog input (v in+ ? v in? above v ref with span compression disabled and above 0.8 v ref with span compression enabled). 2 this output code is also the code for an underranged analog input ( v in+ ? v in? below ?v ref with span compression disabled and below ?0.8 v ref with span compression enabled).
data sheet ad4001/ad4005 rev. b | page 19 of 37 applications informa tion typical application diagram s figure 32 shows an example of the recommended connection diagram for the ad4001 / ad4005 when multiple supplies are available. this configuration is used for best performance because the amplifier suppli es can be selected to allow the maximum signal range. f igure 33 shows a recommended connection diagram when using a single - supply system. this setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. f igure 34 shows a recommended connection diagram when using a fully differential amplifier. c r v+ ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001/ad4005 3-wire/4-wire interface 1.8v 1.8v to 5v v+ +6.5v digital host (microprocessor/ fpga) v? ?0.5v host supply 0.1f 0.1f 5v c r v? v+ v? amp amp v ref 0v v ref 0v v cm = v ref /2 v cm = v ref /2 ref ldo amp v cm = v ref /2 10f 10k 10k 15368-009 figure 32 . typical application diagram with multiple supplies c r ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001/ad4005 2 1.8v 1.8v to 5v v+ = +5v digital host (microprocessor/ fpga) host supply 0.1f 0.1f 100nf 100nf 4.096v c r amp amp 0.9 v ref 0.1 v ref 0.9 v ref 0.1 v ref v cm = v ref /2 v cm = v ref /2 ref 1 ldo amp v cm = v ref /2 10f 1 10k 10k 1 see the voltage reference input section for reference selection. c ref is usually a 10f ceramic capacitor (x7r). 2 span compression mode enabled. 3 see table 10 for rc filter and amplifier selection. 3-wire/4-wire interface 3 15368-010 f igure 33 . typical application diagram with a single supply
ad4001/ad4005 data sheet rev. b | page 20 of 37 10f ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001/ad4005 3-wire/4-wire interface 1.8v 1.8v to 5v digital host (microprocessor/ fpga) 4.096v 0.1f v ocm r3 1k? +in v+ ?in ?out +out r4 1k? 10k 10k r2 1k? r r differential amplifier r1 1k? 0.1f v cm = v ref /2 host supply v? c c ref v+ = +5v ldo amp v ref 0 v cm = v ref /2 v ref 0 v cm = v ref /2 0.1f v cm = v ref /2 15368-0 1 1 f igure 34 . typical application diagram with a fully differential amplifier ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001/ad4005 1.8v to 5v +in ?in r4 1k? differential amplifier r1 1k? v? amp +v ref ?v ref 0v 1.8v 10f r 3 1k ? v+ ?out +out r2 1k? r r 0.1f v ref /2 host supply c c ref v+ = +5v ldo 10k 10k v ocm 4.096v 0.1f 0.1f 3-wire/4-wire interface digital host (microprocessor/ fpga) v cm = v ref /2 15368-012 figure 35 . typical application diagram for single - ended to differential conversion with a fully differential amplifier analog inputs figure 36 shows an equivalent circuit of the analog input structure , including the overvoltage clamp of the ad4001 / ad4005 . c ext r ext v in ref d1 in+/in? gnd clamp 0v to 15v r in c in d2 c pin 15368-013 figure 36 . equivalent analog input circuit input over v oltage clamp circuit most adc analog inputs, in+ and in?, have no overvoltage protection circuitry apart from esd protection diodes. during an overvoltage event, an esd protection diode from an analog input (in+ or in?) pin to ref forward biases and shorts the input pin to ref, po tentially overloading the reference or causing damage to the device. the ad4001 / ad4005 internal overvoltag e clamp circuit with a larger external resistor (r ext = 200 ?) eliminates the need for external protection diodes and protects the adc inputs against dc overvoltages. in applications where the amplifier rails are greater than v ref and less than ground , it is possible for the output to exceed the input voltage range of the device. in this case, the ad4001 / ad4005 internal voltage clamp circuit ensures that the voltag e on the input pin does not exceed v ref + 0.4 v and prevents damage to
data sheet ad4001/ad4005 rev. b | page 21 of 37 the device by clamping the input voltage in a safe operating range and avoid ing disturbance of the reference , which is particularly important for systems that share the reference among multiple adcs. if the analog input exceeds the reference voltage by 0.4 v, t h e internal clamp circuit turns on and the current flows through the clamp into ground, preventin g the input from rising further and potentially causing damage to the device. the clamp turns o n before d1 (see figure 36) and can sink up to 50 ma of current. when th e clamp is active, it sets the ov clamp flag bit in the register that can be read back (see table 14 ), which is a sticky bit that must be read to be cleared. the status of the clamp can also be checked in the status bits using an overvoltage clamp flag (see table 15 ). the clamp circuit does not dissipate static power in the off state. note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. the external rc filter is usually present at the adc input to band limit the i nput signal. during an overvoltage event, excessive voltage is dropped across r ext , and r ext becomes part of a protection circuit. the r ext value can vary from 200 ? to 20 k? for 15 v protection. the c ext value can be as low as 100 pf for c orrect operation of the clamp. see table 1 for input overvoltage clamp specifications. differential input c onsiderations the analog input structure allows the sampling of the true differential signal between in+ and in?. by using thes e differentia l inputs, signals common to both inputs are rejected. figure 37 shows the common - mode rejection capability of the ad4001 / ad4005 over frequency. it is important to note that the differential i nput signals must be truly anti phase in nature , 180 out of phase , which is required to keep the common - mode voltage of the input s ignal within the specified range around v ref /2 as shown in table 1 . 72 71 70 69 68 67 66 cmrr (db) 100 1k 10k 100k 1m frequency (hz) 15368-303 figure 37 . cmrr vs . frequency, v dd = 1.8 v, v io = 3.3 v, v ref = 5 v, 25c switched capacitor input during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin an d the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance . r in is typically 4 00 ? and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 40 pf and is mai nly the adc sampling capacitor. during the conversion phase, where the switches are open , the input impedance is limited to c pin . r in and c in make a single - pole, low - pass filter that reduces undesirable aliasing effects and limits noise. rc f ilter v alues the r c filter value (represented by r and c in figure 32 to figure 35) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. lower input signal bandwidth means that the rc cutoff can be lower , thereby reducing noise into the converter. for optimum performance at various throughput s , use the recommended rc values (200 ?, 180 pf) and the ada4807 - 1 . the rc values shown i n table 10 are chosen for ease of drive considerations and greater adc input protection. the combination of a large r value (200 ? ) and small c value result s in a reduced dynamic load for the amplifier to drive. the smaller value of c means fewer stability and phase margin concerns with the amplifier. the large value of r limit s the current into the adc input when the amplifier outp ut exceeds the adc input ran ge. table 10 . rc filter and amplifier selection for various input ba ndwidths input signal bandwidth (h) r () c (pf) recommended amplifier recommended fully differential amplifier <10 see the high - z mode section ada4940 - 1 <200 200 180 ada4807 -1 ada4940 -1 >200 200 120 ada4897 -1 ada4932 -1 multiplexed 200 120 ada4897 -1 ada4932 -1
ad4001/ad4005 data sheet rev. b | page 22 of 37 driver amplifier cho ice although the ad4001 / ad4005 are easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept low enough to preserve the snr and transition noise performance of the ad4001 / ad4005 . the noise from the driver is filtered by the single - pole, low - pass filter of the ad4001 / ad4005 analog input circuit made by r in and c in , or by the external filter, if one is used. because the typical noise of the ad4001 / ad4005 is 54 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 4 5 v 54 log 20 n db 3 loss ne f v snr ee f ? 3 db is the input bandwidth, in megahertz, of the ad4001 / ad4005 ( 10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent in put noise volt age of the op amp in nv/hz. ? for ac applications, the driver must have a thd performance commensurate with the ad4001 / ad4005 . ? for multichannel multiplexed applications, the driver amplifier and the analog input circuit of the ad4001 / ad4005 must settle for a full - scale ste p onto the capacitor array at a 1 6 - bit level ( 0.0001525%, 15.25 ppm ). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this settling may differ significantly from the settling time at a 1 6 - bit le vel and must be verified prior to driver selection. single to differential driver for applications using a single - ended analog signal, either bipolar or unipolar, the ada4940 - 1 single - ended to differential driver allows a differential input to the device . the schematic is shown in figure 35. high frequency input signals the ad4001 / ad4005 ac performance over a wide input frequency range (using a 5 v reference voltage) is shown in figure 38 and figure 39. unlike other traditional sar adcs, the ad4001 / ad4005 maintain exceptional ac performance for input frequencies up to the nyquist frequency with minimal performance degradation. note that the input frequency is limited to the nyquist frequency of the sample rate in use. 15368-2 1 1 14.0 14.2 14.4 14.6 14.8 15.0 15.2 15.4 15.6 15.8 88 89 90 91 92 93 94 95 96 97 srn, sinad (db) snr sinad enob 1k 10k 100k 1m input frequency (hz) figure 38 . snr, sinad , and enob vs. input frequ e ncy , v dd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c 1k 10k 100k 1m input frequency (hz) sfdr (db) thd (db) 15368-214 90 95 100 105 1 10 1 15 120 125 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 thd sfdr figure 39 . thd and sfdr vs. input frequen cy , v dd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c multiplexed applications the ad4001 / ad4005 significantly reduce system complexity and cost for multiplexed applications that require superior performance in terms of noise, power, and throughput. figure 40 shows a simplified block diagram of a multiplexed data acquisition system including a multiplexer, an adc driver, and the precision sar adc. 15368-539 sar adc adc driver multiplexer sensors r r r c c c c figure 40 . multiplexed data acquisition signal chain using the ad4001 / ad4005 switching multiplexer channels typically results in large voltage steps at the adc inputs. to ensure an accurate conversion result, the step must be given adequate time to settle before the adc samples its inputs (on the rising edge of cnv). the settling time error is dependent on the drive circuitry (multiplexer and adc driver), rc filter values, and the time when the multiplexer
data sheet ad4001/ad4005 rev. b | page 23 of 37 cha nnels are switched. switch the multiplexer channels immediately after t quiet1 has elapsed from the start of the conversion to maximize settling time while preventing corruption of the conversion result. to avoid conversion corruption, do not switch the cha nnels during the t quiet1 time. if the analog inputs are multiplexed during the quiet conversion time (t quiet1 ), the current conversion may be corrupted. ease of drive featur es input span compression in single - supply applications, it is desirable to use the full range of the adc; however, the amplifier can have some headroom and footroom requirements, which can be a problem, even if it is a rail - to - rail input and output amplifier. the ad4001 / ad4005 include a span compression increases the headroom and footroom available to the amplifier by reducing the input range by 10% from the top and bottom of the range while still ac cessing a ll available adc codes ( see figure 41 ) . the snr decreases by approximately 1.9 db (20 l og(8/10)) for the reduced input range when span compression is enabled. span compression is disabled by default but can be enabled by writing to the relevant register bit ( see the digital interface section ) . adc v ref = 4.096v digital output all 2 n codes +fsr ?fsr 90% of v ref = 3.69v 10% of v ref = 0.41v analog input 5v in+/in? 15368-300 figure 41 . span compression high - z m ode the ad4001 / ad4005 incorporate high - z mode , which reduces the non linear charge kickback when the capacitor dac switches back to the input at the start of acquisition. figure 42 shows the input curre nt of the ad4001 / ad4005 with h igh - z mode enabled and disabled. the low input current makes the adc easier to drive than the traditional sar adcs available in the market , even with high - z mode disabled. the input current reduces further to s ubmicroampere range when high - z mode is enabled. the hig h - z mode is disabled by default but can be enabled by writing to the register (see tabl e 14 ). disable high- z mode for input frequencies above 100 khz or when multiplexing. ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 15 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 input current (a) input differentia l vo lt age (v) high-z disabled, 2msps high-z disabled, 1msps high-z enabled, 2msps high-z enabled, 1msps 15368-301 figure 42 . input current vs . input differenti al voltage , v dd = 1.8 v, vio = 3.3 v, v ref = 5 v , 25c to achieve the optimum data sheet performance from high resolution precision sar adcs, system designers are often forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor sar adc inputs for thei r precision applications, which is commonly encountered in designing a precision data acquisition signal chain. the benefits of high - z mode are low input current for slow (<10 k hz) or dc type signals and improved distortion (thd) performance over a frequen cy range of up to 100 khz. high - z mode allows a choice of lower power and lower bandwidth precision amplifiers with a lower rc filter cutoff to drive the adc , removing the need for dedicated high speed adc drivers, which sav es system power, size , and cost in precision, low bandwidth applications. high - z mode allows the amplifier and rc filter in front of the adc to be chosen based on the signal bandwidth of interest an d not based on the settling requirements of the switched capacitor sar adc inputs. additionally , the ad4001 / ad4005 can be driven with a much higher source impedance than traditional sars , which means the resis t or in the rc filter can have a value 10 times larger than previous sar designs and , with h igh - z mode enabled , can tolerate even larger impedance. figure 43 shows the thd performance for various source impedances with hi gh - z mode disabled and enabled.
ad4001/ad4005 data sheet rev. b | page 24 of 37 15368-228 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 1 10 20 input frequency (khz) 150 high-z disabled 150 high-z enabled 510 high-z disabled 510 high-z enabled 1k high-z disabled 1k high-z enabled figure 43 . thd vs . input frequency for various source impedance s , v dd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c figure 44 and figure 45 show the ad4001 / ad4005 snr and thd performance using the ada4077 - 1 ( supply current per amplifier (i sy ) = 400 a ) and ada4610 - 1 ( i sy = 1.5 0 ma) precision amplifiers when driving the ad4001 / ad4005 at full throug hput for high - z mode enabled and disabled with various rc filter values. these amplifiers achieve 9 3 db to 9 6 db typical snr and better than ?110 db thd with high - z mode enabled. thd is approximately 10 db better with high - z mode enabled, even for large r values. snr maintains close to 9 6 db, even with a very low rc bandwidth cutoff. when high - z mode is enabled, the adc consume s approximately 2 mw per msps extra power; however, this power is still significantly lower than using dedicated adc drivers like the ada4807 - 1 . for any sys tem, the front end usually limits the overall ac/dc perf ormance of the signal chain. it is evident from the data sheet s of the selected precision amplifier s, shown in figure 44 and figure 45, that their own noise and distortion performance dominates the snr and thd specification at a certain input frequency. 260khz 1.3k 470pf 498khz 680 470pf 1.3mhz 680 180pf 2.27mhz 390 180pf 4.42mhz 200 180pf rc fi l ter bandwidths (hz), resis t or (), ca p aci t or (pf) 15368-439 73 76 79 82 85 88 91 94 97 snr (db) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled figure 44 . s nr vs. rc filter bandwidth s for v arious precision adc drivers, f in = 1 khz (turbo mode o n , high - z e nabled/ d isabled) , v dd = 1.8 v, vio = 3.3 v , v ref = 5 v, 25c 15368-440 rc fi l ter bandwidths (hz), resis t or (), ca p aci t or (pf) 260khz 1.3k 470pf 498khz 680 470pf 1.3mhz 680 180pf 2.27mhz 390 180pf 4.42mhz 200 180pf ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 thd (db) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled figure 45 . thd vs. rc filter bandwidth s for v arious precision adc drivers, f in = 1 khz (turbo mode o n , high - z e nable d/ d isabled) , v dd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c long acquisition phase the ad4001 / ad4005 also feature a very fast conversion time of 2 9 0 ns , which r esults in a long acquisit ion phase . the acquisition is further extended by a key feature of the ad4001 / ad4005 : th e adc r eturn s to the acquisition phase typically 100 ns before the end of the conversion . this feature provides an even longer time for the adc to acquire the new input voltage. a longer acquisition phase reduces the settling requirement on the driving amplifier , and a lower power/bandwidth amplifier can be chosen. the longer acquisition phase means that a lower rc filter (represented by r and c in figure 32 to figure 35) cutoff can be used , which means a noisier amplifier can also be tolerated. a larger value of r can be used in the rc filter with a corresponding smaller value of c , reducing amplifie r stability concerns without affecting distortion performance significantly. a larger value of r also results in reduced dynamic power dissipation in the amplifier. see table 10 for details on setting the rc filter bandwidth and choosing a suitable amplifier. voltage reference in put a 10 f (x7 r, 0 8 0 5 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input . for higher performance and lower drift , use a reference such as the adr4550 . u se a low power reference such as the adr3450 at the expense of a slight decrease in the noise performance . it is recommended to use a reference buffer , such as the ada480 7 - 1 , between the refere nce and the adc reference input. it is important to consider the optimum capacitance necessary to keep the reference buffer stable as well as to meet the minimum adc requirement previously stated in this section (that is, a 10 f ceramic chip capacitor , c ref ) . power supply the ad4001 / ad4005 use two power supply pins: a core supply (vdd) and a digital input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v.
data sheet ad4001/ad4005 rev. b | page 25 of 37 to reduce the number of supplies needed, vio and vdd can be tied together for 1.8 v operation. the adp7118 low noise, cmos, low dropout (ldo) linear regulator is recommended to power the vdd and vio pins. the ad4001/ ad4005 are independent of power supply sequencing between vio and vdd. additionally, the ad4001/ ad4005 are insensitive to power supply variations over a wide frequency range, as shown in figure 46. 80 75 70 65 60 55 50 psrr (db) 100 1k 10k 100k 1m frequency (hz) 15368-302 figure 46. psrr vs. frequency, v dd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c the ad4001/ ad4005 power down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this feature makes the device ideal for low sampling rates (even a few samples per second) and battery- powered applications. figure 47 shows the ad4001/ ad4005 total power dissipation and individual power dissipation for each rail. 100k 100 10k 1 10 1k 0.1 0.01 power dissipation (w) 10 1m 2m 100k 10k 1k 100 throughput (sps) vdd vio ref total power 15368-220 power dissipation measurements apply to each product over its specified throughput range. figure 47. power dissipa tion vs. throughput, v dd = 1.8 v, vio = 1.8 v, v ref = 5 v, 25c digital interface although the ad4001/ ad4005 have a reduced number of pins, they offer flexibility in their serial interface modes. the ad4001/ ad4005 can also be programmed via 16-bit spi writes to the configuration registers. when in cs mode, the ad4001/ ad4005 are compatible with spi, qspi?, microwire?, digital hosts, and dsps. in this mode, the ad4001 / ad4005 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections, which is useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this interface is useful in low jitter sampling or simultaneous sampling applications. the ad4001/ ad4005 provide a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line, similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and daisy-chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, daisy-chain mode is always selected. in either 3-wire or 4-wire mode, the ad4001/ ad4005 offer the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled in cs mode if cnv or sdi is low when the adc conversion ends. the state of sdo on power-up is either low or high-z depending on the states of cnv and sdi, as shown in in table 11. table 11. state of sdo on power-up cnv sdi sdo 0 0 low 0 1 low 1 0 low 1 1 high-z the ad4001/ ad4005 have turbo mode capability in both 3-wire and 4-wire mode. turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. turbo mode allows a slower spi clock rate, making interfacing simpler. the maximum throughput of 2 msps for the ad4001 can be achieved only with turbo mode enabled and a minimum sck rate of 70 mhz. the sck rate must be sufficiently fast to ensure the conversion result is clocked out before another conversion initiates. the minimum required sck rate for an application can be derived based on the sample period (t cyc ), the number of bits that must be read (including data and optional status bits), and which digital interface mode is used. timing diagrams and explanations for each digital interface mode are given in the digital modes of operation sections (see the cs mode, 3-wire turbo mode section through the daisy-chain mode section). status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. there are six status bits in total, as described in table 12.
ad4001/ad4005 data sheet rev. b | page 26 of 37 the ad4001 / ad4005 are configured by 16 - bit spi writes to the desired configuration register. t he 16 - bit word can be written via the sdi line while cnv is held low . the 16 - bit word consists of an 8 - bit header and 8 - bit register data. for isolated systems, the adum141d is recommende d, which can support the 70 mhz sck rate required to run the ad4001 at its full throughput of 2 msps. register read/write functionality the ad4001 / ad4005 register bits are programmable , and their default status es are shown in table 12 . the register map is show n in table 14. the overvoltage clamp flag ( ov ) is a read only sticky bit , and it is cleared only if the register is read and the overvoltage condition is no longer present. it gives an indication of overvoltage condition when it i s set to 0. table 12 . register bits register bits default status overvoltage ( ov ) clamp flag 1 bit, 1 = inactive (default) span compression 1 bit, 0 = disabled (default) high - z mode 1 bit, 0 = disabled (default) turbo mode 1 bit, 0 = disabled (default) enable six status bits 1 bit, 0 = disabled (default) all access to the register map must start with a write to the 8 - b it command register in the spi interface block. the ad4001 / ad4005 ignore all 1 s until the first 0 is clocked in; the value loaded into th e command register is always a 0 followed by seven command bits. this com mand determines whether that operation is a write or a read. the ad4001 / ad4005 command register is shown in table 13. table 13 . command register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wen r/ w 0 1 0 1 0 0 all register read/writes must occur while cnv is low. data on sdi is clocked in on the rising edge of sck. data on sdo is clocked out on the falling edge of sck. at the end of the data transfer , sdo is put in a high impedance state on the rising edge of cnv if daisy - chain mode is not e nabled . if daisy - chain mode is enabled , sdo goes low on the rising edge of cnv. register reads a re not allowed in daisy - chain mode. a r egister write requires three signal lines: sck, cnv, and sdi. during a register write, to read the current conversion results on sdo, the cnv pin must be brought low after the conversion is completed ; otherwise, the conversion results may be incorrect on sdo . h owever, the register write occur s regardless . the lsb of each configuration register is reserved because a user r eading 16 - bit conversion data may be limited to a 16 - bit spi frame. the state of sdi on the last bit in the sdi frame may be the state that then persists when cnv rises. because interface mode is partly set based on the sdi state when cnv rises, in this sc enario, the user may need to set the final sdi state. the timing diagram s in figure 48 through figure 50 show how data is read and written when the ad4001 / ad4005 are configured in register read, write , and daisy - chain mode. table 14. register map addr [1:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0x0 reserved reserved reserved enable six status bits span compression high -z mode turbo mode overv oltage ( ov ) c lamp f lag (read only sticky bit ) 0x e1 t cyc t sck t dis t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh t en cnv sck 1 2 3 4 5 6 7 0 1 1 0 1 0 1 0 0 b0 b1 b2 b3 b4 b5 b6 wen r/w 0 1 0 1 addr[1:0] 8 9 10 11 12 13 14 15 16 sdi sdo t hsdo t dsdo b7 x d17 d16 d15 d14 d13 d12 d11 d10 15368-021 figure 48 . register read timing diagram (x means dont care)
data sheet ad4001/ad4005 rev. b | page 27 of 37 1 conversion result on d[15:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t cyc t sck t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh 1 en cnv 1 the user must wait t conv when reading back the conversion result and performing a register write at the same time. sck 1 2 3 4 5 0 0 1 0 1 0 1 0 0 wen r/w 0 1 0 1 addr[1:0] 9 10 11 12 13 14 15 16 sdi sdo b0 b1 b2 b3 b4 b5 b6 b7 t hsdo t dsdo t hcnvsck 15368-022 figure 49 . register write timing diagram sdi a sdo a /sdi b sdo b 0 0 command (0x14) 0 0 command (0x14) 0 0 command (0x14) t cyc t sck t sck l t sckh t scnvsck cnv sck 1 24 t dis t cnvh data (0xab) data (0xab) 15368-023 figure 50 . register w rite timing diagram , d aisy - c hain m ode
ad4001/ad4005 data sheet rev. b | page 28 of 37 status word the 6 - bit status word can be appended to the end of a conversion result , and the default conditions of these bits are shown in table 15 . the status bits must be enabled in the register setting. when the ov ervoltage clamp flag ( ov ) is a 0 , it indicat es an overvoltage condition . the overvoltage clamp flag status bit updates on a per conversion basis. the sdo line goes to high - z after the sixth status bit is clocked out (except in daisy - chain mode). the user is not required to clock out all status bits to start the next conversion. the serial interface timing for cs m ode, 3 - w ire without busy indicator , including status bits , is shown in figure 51. table 15. status b its ( d efault condition s ) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 overvoltage ( ov ) clamp flag span compression high - z mode turbo mode reserved reserved sdo d15 d14 d13 d1 d0 sck 1 2 3 14 15 16 t sck t sck l t sckh t hsdo t dsdo cn v conversion acquisition t cyc acquisition sdi = 1 t cnvh acq t en 21 22 t quiet2 status bits b[5:0] b1 t dis b0 20 t conv 15368-024 figure 51 . cs mode, 3 - wire without busy indicator serial interface timing diagram , i ncluding status bits (sdi high)
data sheet ad4001/ad4005 rev. b | page 29 of 37 cs mode, 3- wire turbo mode this mode is typically used when a single ad4001 / ad4005 device is connecte d to an spi - compatible digital host. it provides additiona l time during the end of the adc conversion process to clock out the previous conversion result, providing a l ower sck rate. the ad4001 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 70 mhz. with turbo mode enabled, the ad4005 can also achieve its maximum throughput rate of 1 msps with a minimum sck rate of 22 mhz. the connection diagram is shown in figure 52 , and the corresponding timing diagram is shown in figure 53. this mode replaces the 3 - wire with busy indicator mode by programming the turbo mode bit, bit 1 (see table 14). when sdi is forced high, a rising edge on cnv initiates a conversion. the previous conversion data is available to read after the cnv rising edge. t he user must wait t quiet1 time after cnv is brought high before bringing cnv low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the ad4001 / ad4005 enter the acquisition phase and power down. when cnv goes low, the msb is output to sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. althou gh the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. ad4001/ ad4005 sdi sdo cnv sck convert data in clk digital host vio 15368-125 figure 52 . cs mode, 3 - wire turbo mode connection diagram (sdi high) sdi = 1 t cyc cnv acquisition acquisition t acq t sck t sck l conversion sck d0 d1 d13 d14 d15 sdo t en t hsdo 1 2 3 14 15 16 t dsdo t dis t sckh t quiet1 quiet2 conv 15368-029 figure 53 . cs mode, 3 - wire turbo mode serial interface timing diagram (sdi high)
ad4001/ad4005 data sheet rev. b | page 30 of 37 cs mode, 3- wire without busy in dicator this mode is typically used when a single ad4001 / ad4005 is connected to an spi - compatible digital host. the connection diagram is shown in figure 54 , and the corresponding timing diagram is shown in figure 55 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. after a conversion is initiated, it continues until completion irrespectiv e of the state of cnv. this feature can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then h eld high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the c onversion is complete, the ad4001 / ad4005 enter the acquisition phase and power down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an ac ceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. there must not be any digital activity on sck during the con version. ad4001/ ad4005 sdi sdo cnv sck convert data in clk digital host vio 15368-025 figure 54 . cs mode, 3 - wire without busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 14 15 16 t sck t sck l t sckh hsdo t dsdo cnv conversion acquisition t cyc acquisition sdi = 1 t cnvh t acq t en t quiet2 t conv 15368-026 figure 55 . cs mode, 3 - wire without busy indicator serial interface timing diagram (sdi high)
data sheet ad4001/ad4005 rev. b | page 31 of 37 cs mode, 3-wire with busy indicator this mode is typically used when a single ad4001 / ad4005 is connected to an spi-compatible digital host with an interrupt input ( irq ). the connection diagram is shown in figure 56, and the corresponding timing diagram is shown in figure 57. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can select other spi devices, such as analog multiplexers; however, cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up resistor of 1 k on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad4001/ ad4005 then enter the acquisition phase and power down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad4001/ ad4005 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. there must not be any digital activity on the sck during the conversion. sdi sdo cnv sck convert data in clk digital host vio irq vio 1k? 15368-027 ad4001/ ad4005 figure 56. cs mode, 3-wire with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t quiet2 15368-028 figure 57. cs mode, 3-wire with busy indicator serial interface timing diagram (sdi high)
ad4001/ad4005 data sheet rev. b | page 32 of 37 cs mode, 4-wire turbo mode this mode is typically used when a single ad4001 / ad4005 device is connected to an spi-compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result, giving a lower sck rate. the ad4001 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 70 mhz. with turbo mode enabled, the ad4005 can also achieve its maximum throughput rate of 1 msps with a minimum sck rate of 22 mhz. the connection diagram is shown in figure 58, and the corresponding timing diagram is shown in figure 59. this mode replaces the 4-wire with busy indicator mode by programming the turbo mode bit, bit 1 (see table 14). with sdi high, a rising edge on cnv initiates a conversion. the previous conversion data is available to read after the cnv rising edge. the user must wait t quiet1 time after cnv is brought high before bringing sdi low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the ad4001/ ad4005 enter the acquisition phase and power down. the adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance. sdi sdo cnv sck convert data in clk digital host irq vio 1k ? cs1 15368-032 ad4001/ ad4005 figure 58. cs mode, 4-wire turbo mode connection diagram acquisition sdo sck acquisition sdi cnv t ssdicnv t hsdicnv t cyc t sck t sckl t en t hsdo 123 1 4 1 51 6 t dsdo t dis t sckh d15 d14 d13 d1 d0 t quiet1 t quiet2 t acq conversion t conv 15368-034 figure 59. cs mode, 4-wire turbo mode timing diagram
data sheet ad4001/ad4005 rev. b | page 33 of 37 cs mode, 4-wire without busy indicator this mode is typically used when multiple ad4001/ ad4005 devices are connected to an spi-compatible digital host. a connection diagram example using two ad4001/ ad4005 devices is shown in figure 60, and the corresponding timing diagram is shown in figure 61. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers; however, sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad4001/ ad4005 enter the acquisition phase and power down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another ad4001/ ad4005 can be read. sdi sdo cnv sck sdi sdo cnv sck device b device a convert data in clk digital host cs1 cs2 15368-030 ad4001/ ad4005 ad4001/ ad4005 figure 60. cs mode, 4-wire without busy indicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 12 3 30 31 32 t hsdo t dsdo t en conversion a cquisition t conv cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sck l t sckh d0 d15 d14 17 18 16 sdi(cs2) t quiet2 15368-031 figure 61. cs mode, 4-wire without busy indicator serial interface timing diagram
ad4001/ad4005 data sheet rev. b | page 34 of 37 cs mode, 4-wire with busy indicator this mode is typically used when a ad4001/ ad4005 device is connected to an spi-compatible digital host with an interrupt input ( irq ), and when it is desired to keep cnv, which samples the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 62, and the corresponding timing diagram is shown in figure 63. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers; however, sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up resistor of 1 k on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad4001/ ad4005 then enter the acquisition phase and power down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance. sdi sdo cnv sck convert data in clk digital host irq vio 1k ? cs1 15368-132 ad4001/ ad4005 figure 62. cs mode, 4-wire with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv t quiet2 15368-033 figure 63. cs mode, 4-wire with busy indicator serial interface timing diagram
data sheet ad4001/ad4005 rev. b | page 35 of 37 daisy - chain mode use t his mode to daisy - chain multip le ad4001 / ad4005 device s on a 3 - wire or 4 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for sy stems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad4001 / ad4005 device s is shown in figure 64 , and the corresponding timing diagram is shown in figure 65 . when sdi and cnv are low , sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects daisy - chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is c omplete, the msb is output onto sdo , and the ad4001 / ad4005 enter the acquisition phase and power down. the remaining data bits stored in the internal shift register are clocked out of sdo by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck rising edge s . each adc in the daisy - chain outputs its data msb first, and 1 6 n clocks are required to read back the n adcs. the data is valid on both sck edges. the maximum conversion rate is reduced because of the total readback time. it is possible to write to each adc register in daisy - chain mode. the timing diagram is shown in figure 50 . this mode requires 4 - wire operation because data is clocked in on the sdi line with cnv held low. the same command byte and regist er data can be shifted through the entire chain to program all adcs in the chain with the same register contents , which requires 8 (n + 1) clocks for n adcs. it is possible to write different register contents to each adc in the chain by writing to the furthest adc in the chain , first using 8 (n + 1) clocks , and then the second furthest adc with 8 n clocks , and so forth until reaching the nearest adc in the chain , which require s 16 clocks for the command and register data . it is not possible to read register con tents in daisy - chain mode ; however, the six status bits can be enabled if the user wants to determine the adc configuration. note that enabling the status bits requires six extra clocks to clock out the adc result and the status bits per adc in the chain . turbo mode cannot be used in daisy - chain mode. convert data in clk digital host device b device a ad4001/ ad4005 ad4001/ ad4005 sdi sdo cnv sck sdi sdo cnv sck 15368-036 figure 64 . daisy - c hain mode connection diagram sdo a = sdi b d a 15 d b 15 d b 14 d b 13 d a 14 d a 13 d a 1 d a 0 d a 1 d a 0 d b 1 d b 0 sck 1 2 3 30 31 32 t ssdisck t hsdisck conversion acquisition t conv t cyc t acq acquisition cnv 14 15 t sck t sck l t sckh 17 18 16 sdi a = 0 sdo b d a 15 d a 14 t hsdo t dsdo t quiet2 t hsckcnv t dis t quiet2 t en 15368-037 figure 65 . daisy - chain mode serial interface timing diagram
ad4001/ad4005 data sheet rev. b | page 36 of 37 layout guidelines the pcb that houses the ad4001 / ad4005 must be designed so that the analog and digital sections are separated and confined to certain areas of th e board. the pinout of the ad4001 / ad4005 , with its analo g signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because the y coup le noise onto the die, unles s a ground plane under the ad4001 / ad4005 is used as a shield. fast switching signals, such as cnv or clocks, must not run near analog signal paths. avoid c rossover of digital and analog signals. at least one ground plane must be used. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the ad4001 / ad4005 device s. the ad4001 / ad4005 voltage reference input ( ref ) has a dynamic input imp edance . d ecouple the ref pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to ( ideally right up against ) the ref and gnd pins and connect them with wide, low impedance traces. finally, decouple the vdd and vio power s upplies of the ad4001 / ad4005 with ceramic capacitors, typically 0.1 f , placed close to the ad4001 / ad4005 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glit ches on the power supply lines. an example of the ad4001 layout following these rules is shown in figure 66 and figure 67 . note that the ad4005 layout is equivalent to the ad4001 layout . 15368-038 figure 66 . e xample layout of the ad4001 (top layer) 15368-039 figure 67 . example layout of the ad4001 (bottom layer) evaluating the ad4001 / ad4005 performance other r ecommended layouts for the ad4001 / ad4005 are outlined in the user guide of th e evaluation board for the ad4001 ( e va l - ad4001 fmcz ). the evaluation board packag e includes a fully assembled and tested evaluation board with the ad4001 documentation, and software for controlling the board from a pc via the e va l - sdp - ch1z . the e va l - ad4001fmcz can also be used to evaluate the ad4005 by limiting t he throughput to 1 msps in its software (see ug - 1042) .
data sheet ad4001/ad4005 rev. b | page 37 of 37 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 68 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 coplanarity 0.08 top view side view bottom vie w 0.20 min pkg-004362 02-07-2017-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 indic at or area options (see detail a) detail a (jedec 95) figure 69 . 10 - lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 , 2 integral nonlinearity (inl) temperature range package description ordering quantity package option branding ad4001bcpz- rl7 0.4 lsb ?40c to +125c 10- lead lfcsp , reel 1500 cp-10-9 c8h ad4001brmz 0.4 lsb ?40c to +125c 10- lead msop , tube 50 rm -10 c8h ad4001brmz- rl7 0.4 lsb ?40c to +125c 10- lead msop , reel 1000 rm -10 c8h ad4005bcpz- rl7 0.4 lsb ?40c to +125c 10- lead lfcsp , reel 1500 cp-10-9 c8t ad4005brmz 0.4 lsb ?40c to +125c 10- lead msop , tube 50 rm -10 c8t ad4005brmz- rl7 0.4 lsb ?40c to +125c 10- lead msop , reel 1000 rm -10 c8t eval -ad4001fmcz ad4001 evaluation board compatible with eval -sdp-ch1z 1 z = rohs compliant part. 2 the eval - ad4001fmcz can also be used to evaluate the ad4005 by setting the throughput to 1 msps in its software (see ug - 1042). ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d15368 -0- 8/17(b)

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